The newer model, C3, C6, C5 all have RSIC-V cores which make it a dream to run Rust (basically: rustup target add riscv32imac-unknown-none-elf).
Here is a good introduction: https://kerkour.com/introduction-to-embedded-development-wit...
Anecdote about this summary at the bottom: > This setup gives you the best of both worlds: ESP-IDF and FreeRTOS manage Wi-Fi, BLE, and system tasks on Core 0, while Core 1 runs your bare-metal Rust code at full speed with zero scheduler interference.
I am doing something somewhat like this, but with separate MCUs instead of separate cores. I flashed Esp-Hosted-MCU onto an ESP-32 (C3, but any including S3 will work). This is official firmware which turns the ESP into a "radio co-processor", so you can treat it like a SPI or UART Wi-Fi/BLE chip.
On another MCU (STM32), I run bare-metal firmware in rust which talks to the radio over SPI. Wi-Fi uses the ESP IDF, and BLE uses standard HCI commands.
Kinda funny because the ESP8266 basically started off as a WiFi "co-processor" with AT commands sent over UART. People quickly discovered it had a good amount of power and you could run your entire application on the ESP8266 instead of using it as a co-processor. That led to an explosion in popularity for "makers" because the chip was so cheap and capable for projects at the time, and I think that led to the ESP32 becoming so widely known.
I did glance at the readme and get the impression that hosted-MCU works for all compatible ESPs and seems more flexible and powerful, where ESP-AT is for select ESP chips and is more limited.
[1]: https://tingouw.com/blog/cloud_notes/badwater_intro#day-5-8m...
This depends on what resources you're counting. If you're counting the developer cycles, it is not.
ESP-IDF+FreeRTOS has great value: it solves a host of mundane problems that need solving in real products. Discarding all of that value is foolish; you should preserve it, and keep your work aligned with the recent ESP-IDF and FreeRTOS evolution.
However, you also want to write actual real time, bare metal code, and you need to do this with hardware peripherals, tight ISRs that aren't ever going to get preempted, and precision memory management. Most of all, you do not want to ever have to rework it because something in ESP-IDF and/or FreeRTOS changed, because they're both rapidly moving targets.
Dedicating cores (0 for FreeRTOS, 1 for you) provides exactly this, and why ESP-IDF supports this model.
For instance, compare the reference manuals for the STM32WL3R and the STM32WB microcontrollers. The former has a single CPU, and it has almost 250 pages of detailed documentation about exactly how the hardware is controlled at a register level. The latter runs the network stack on an auxiliary CPU, and the manual just has a block diagram and a sentence that says "use our drivers" (which are only available in encrypted format).